A technique is known in which, using a method similar to the method for forming a circuit shape by using a copper clad laminate, a capacitor structure is formed in a printed wiring board, in particular, an inner layer portion of a multilayer printed wiring board, and the capacitor structure is used as an embedded capacitor. By forming the capacitor structure in the inner layer portion of the multilayer printed wiring board, it is possible to omit a capacitor provided on an outer layer surface, and achieve an outer layer circuit with a finer structure and higher density. As a result, the number of surface mounted components is reduced, which makes it easy to produce a printed wiring board including a fine pitch circuit.
The multilayer printed wiring board with an embedded capacitor described above is produced by, as disclosed in, for example, Patent Literature 1, using a double-sided copper clad laminate composed of a pair of copper foil layers and a dielectric layer provided between the copper foil layers, and etching the copper foil layer on each side into a capacitor electrode that has a desired shape. However, with the double-sided copper clad laminate disclosed in Patent Literature 1, the dielectric layer is brittle. Accordingly, the dielectric layer may be damaged if an excessively high external force is applied during the production process.
The method as shown in FIGS. 8(a) to 8(f) is known as an example of a method for producing a multilayer printed wiring board that addresses the problem described above. According to the method shown in FIGS. 8(a) to 8(f), first, as shown in FIG. 8(a), a carrier attached copper foil 115s is arranged on each surface of a resin substrate 121 to obtain a support member 100. The carrier attached copper foils 115s are arranged on the resin substrate 121 in such a manner that a carrier 113s of each carrier attached copper foil 115s faces the resin substrate 121.
Next, as shown in FIG. 8(b), a dielectric-carrier attached copper foil is arranged on each surface of the support member 100 in this state, each dielectric-carrier attached copper foil being a laminate of a carrier attached copper foil 115c and a dielectric layer 111. Each carrier attached copper foil 115c is arranged on the support member 100 in such a manner that the dielectric layer 111 faces a copper foil 112s included in the support member 100. In this way, a laminated member 120 is obtained. The dielectric layers 111 before being stacked contain a thermosetting resin in the B stage.
In each of the obtained laminated members 120, as shown in FIG. 8(c), a carrier 113c included in the carrier attached copper foil 115c is released so as to expose the copper foil 112s to the surface, and the exposed copper foil 112 is etched. By doing so, a conductor pattern 130 is formed as shown in FIG. 8(c). Next, as shown in FIG. 8(d), an insulating layer 135 is arranged on each of the conductor patterns 130, and a copper layer 137 is arranged on each of the insulating layers 135. Then, as shown in FIG. 8(e), separation is performed between the carriers 113c and copper foils 112s in the support member 100.